1. Field of the Disclosure
The present disclosure generally relates to processing systems and more particularly to power state transitions for processing systems.
2. Description of the Related Art
Processing systems often implement one or more sleep states to reduce power consumption during periods of relative inactivity. Some of these sleep states involve removing one or more components of a processor device, or the entire processor device, from power, which necessitates reinitialization of the processor device upon exiting the sleep state before the operating system can resume control. This reinitialization conventionally is performed in the same manner as an initialization from a power-on reset, also called a “cold boot,” which involves the execution of basic input/output system (BIOS) code accessed from a non-volatile memory external to the processor device. The access of the BIOS code from the non-volatile memory often is relatively slow and thus is a significant contributor to the relatively long wake-up latency exhibited by conventional processing systems when exiting such sleep states.
The use of the same reference symbols in different drawings indicates similar or identical items.